A DRAM memory cell comprises a storage capacitor and a field effect transistor, the channel of which couples a storage node junction (which is coupled to one plate of the capacitor) and an Access node junction (which is coupled to a bitline). In DRAM cells utilizing a conventional planar capacitor, far more chip surface area is dedicated to the planar capacitor than to the field-effect transistor (FET). Wordlines are generally etched from a first doped polycrystalline silicon (hereinafter, "polysilicon" or "poly") layer. A doped region of silicon substrate functions as the lower (storage-node) capacitor plate, while a second doped polysilicon layer generally functions as the upper capacitor plate (cell plate). Although planar capacitors have generally proven adequate for use in DRAM chips up to the one-megabit level, they are considered to be unusable for more advanced DRAM generations. As component density in memory chips has increased, the shrinkage of cell capacitor size has resulted in a number of problems. Firstly, the alpha-particle component of normal background radiation can generate hole-electron pairs in the silicon substrate, which functions as the lower capacitor plate. This phenomena will cause a charge stored within the affected cell capacitor to rapidly dissipate, resulting in a "soft" error. Secondly, the sense-amplifier differential signal is reduced. This aggravates noise sensitivity and makes it more difficult to design column sense-amplifiers having appropriate signal selectivity. Thirdly, as cell capacitor size is decreased, the cell refresh time must generally be shortened, thus requiring more frequent interruptions for refresh overhead. The difficult goal of a DRAM designer is therefore to increase or, at least, maintain cell capacitance as cell size shrinks, without resorting to processes that reduce product yield or that markedly increase the number of masking and deposition steps in the production process.
As a result of the problems associated with the use of planar capacitors for high-density DRAM memories, all manufacturers of 4-megabit DRAMs are utilizing cell designs based on non-planar capacitors. Two basic non-planar capacitor designs are currently in use: the trench capacitor, and the stacked capacitor. Both types of non-planar capacitors typically require a considerably greater number of masking, deposition and etching steps for their manufacture than does a planar capacitor.
In a trench capacitor, charge is stored primarily vertically, as opposed to horizontally as in a planar capacitor. Since trench capacitors are fabricated in trenches which are etched in the substrate, the early trench capacitors, like planar capacitors, were particularly susceptible to soft errors. In addition, there are several other problems inherent in the trench design. One problem is that of trench-to-trench charge leakage, caused by the parasitic transistor effect between adjacent trenches. Another problem is capacitor leakage related to defects in the substrate crystal structure induced, primarily, by the trench etch itself, stresses inherent in the bird's beak region (the field oxide edge), or by thermal cycling during processing. Another problem of trench capacitors is the ineffectiveness of "Hi-C" boron implants. If the trench walls are implanted with an angled implant, the implanted boron will diffuse into the channel and disrupt transistor function. Another problem is the difficulty of completely cleaning the trenches during the fabrication process; failure to completely clean a trench will generally result in a defective cell.
The stacked capacitor design, on the other hand, has proven somewhat more reliable and easier to fabricate than the trench design. Since both the lower and the upper plates of a typical stacked capacitor are formed from individual conductive layers, the stacked capacitor is generally much less susceptible to soft errors than either the planar or trench capacitors. By placing the wordline and, in some designs, also the digitline beneath the capacitive layers, and having the lower layer make contact with the substrate by means of a buried contact, some manufacturers have created stacked capacitor designs in which vertical portions of the capacitor contribute significantly to the total charge storing capacity. Since a stacked capacitor generally covers not only the entire area of a cell (including the cell's access FET), but adjacent field oxide regions as well, capacitance is considerably enhanced over that available from a planar type cell.
Although the stacked cell capacitor has proven to be the most manufacturable design for the four-megabit generation, trenches are generally considered to be a good bet for future generations, due to the fact that trenches can be made deeper for increased capacitance, without affecting topography of the array. However, the continuing development of new technology makes it impossible to reliably predict the design of future DRAM generations. For example, the problems of crystal defect-related capacitor leakage and high soft error rate, which were characteristic of early trench designs has been solved by lining the trenches with a dielectric material and using a deposited conductive layer for the storage-node plate. This technique also eliminates the need for a Hi-C boron implant. Nevertheless, advances in stacked capacitor technology promise to make that design a participant in the 64-megabit generation. For example, complex three-dimensional structures have been created that greatly increase storage-node plate surface area. Generally, however, such structures require complex processing and multiple photomasks.
The electrodes, or plates, of a stacked capacitor are typically patterned from individual layers of conductively-doped polycrystalline silicon (hereinafter also "polysilicon"). One problem related to the use of a conductively-doped polysilicon layer for the bottom plate of a DRAM capacitor is that, unless the storage-node plate contact with the substrate is made a considerable distance from the cell access transistor, the dopant impurities from the polysilicon storage-node plate will tend to diffuse into the channel of the cell access transistor, resulting in lowered threshold voltages and high leakage current through the transistor when the gate is not activated.
A new capacitor design, which incorporates aspects of both the stacked and trench designs in order to further increase capacitor plate area, has recently been receiving considerable attention in the DRAM industry. Like the stacked capacitor, the new capacitor utilizes deposited conductive layers for both capacitor plates. However, in the stacked-trench capacitor, the storage-node plate lines a trench in the substrate in addition to covering the wordline. The stacked trench capacitor has an advantage of allowing increased capacitance for a given level of integration over either a simple stack or trench capacitors.
The most space-efficient way of making a stacked-trench capacitor is to etch the trench so that it is self-aligned both to an adjacent field oxide region and to the vertical edge of the access transistor gate spacer. There are several problems associated with self-aligned trenches. If the capacitor has a phosphorus-doped polycrystalline silicon storage-node capacitor plate, such a structure is particularly susceptible to the outdiffusion of phosphorus from the storage-node plate into the channel region of the adjacent access transistor, resulting in lowered access transistor threshold voltages and high leakage current. In-situ, arsenic doping of the capacitors polysilicon storage node plate (the plate which is in intimate contact with the access transistor's storage node junction) greatly mitigates the outdiffusion problem. Another problem is the difficulty of making contact between the capacitor's storage node plate if the trench is lined with a dielectric material in order to insulate the storage node plate from the substrate, and thus minimize the area exposed to alpha particle radiation hits.